1. Field of the Invention
The present invention broadly relates to a semiconductor storage device using polarization of a ferroelectric substance. More specifically, the present invention relates to a reference potential generation circuit used in a ferroelectric memory circuit for determining a data state of a memory cell comprising one transistor and one ferroelectric capacitor.
2. Description of the Background Art
The semiconductor storage device using a ferroelectric capacitor is a storage device that uses spontaneous polarization characteristics attributed to a ferroelectric substance used as a capacity insulating film of the capacitor. Accordingly, there is an advantage of eliminating the need for a refresh operation needed for DRAM (Dynamic Random Access Memory) as a conventional semiconductor storage device. Another advantage is to prevent data stored in a memory cell from being lost independently of a power supply state.
A memory cell using the ferroelectric substance comprises one MOS (Metal Oxide Semiconductor) transistor and one ferroelectric capacitor (1T/1C). This configuration has been conventionally employed for DRAM. As another configuration, such memory cell comprises two MOS transistors and two ferroelectric capacitors (2T/2C). Since there is an increasing need for miniaturization and large-scale integration of semiconductor devices in recent years, particular attention is paid to memory cells having the 1T/1C structure as the memory cell configuration.
A semiconductor storage device using a ferroelectric memory cell having the 1T/1C structure decreases an area required for each cell and is appropriate for large-scale integration. When data is read from a memory cell, However, such semiconductor storage device requires a reference potential for amplifying a signal of the memory cell. Namely, it is necessary to provide a reference potential generation circuit for generating the reference potential.
For example, a conventional reference potential generation circuit is depicted in FIG. 6.
FIG. 6 shows a conventional example. The conventional reference potential generation circuit comprises a pair of a bit line BL and a bit complementation line BLb; reference cells RMC0 through RMC3 respectively connected to the bit line BL or the bit complementation line BLb; a reference word line RWL; a reference plate line RPL; a reference write signal line RWSL0 connected to a fixed potential; and a reference write signal line RWSL1 supplied with a power supply potential Vdd.
Each of reference cells RMC0 through RMC3 is arranged at an intersecting point between each bit line and reference word line.
Of the reference cells RMC0 through RMC3, the reference cells RMC0 and RMC2 are connected to bit lines BL0 and BL1, respectively. The reference cells RMC0 and RMC2 respectively comprise selection transistors RT0 and RT2 operated by a reference word line RWL1; and ferroelectric capacitors H0 and H2 in each of which one terminal is connected to the selection transistor RT0 or RT2 and the other terminal is connected to the reference plate line RPL. The reference cells RMC1 and RMC3 are connected to bit complementation lines BLb0 and BLb1, respectively. The reference cells RMC1 and RMC3 respectively comprise selection transistors RT1 and RT3 operated by a reference word line RWL0; and ferroelectric capacitors H1 and H3 in each of which one terminal is connected to the selection transistor RT1 or RT3 and the other terminal is connected to the reference plate line RPL.
The reference cells RMC0 through RMC3 are connected to the reference write signal line RWSL0 connected to a ground potential Vss or the reference write signal line RWSL1 connected to the power supply potential Vdd via switch transistors T0 through T3.
A switch transistor T4 is connected between two bit lines BL to which the reference cells RMC1 and RMC3 are connected. A switch transistor T5 is connected between two bit complementation lines BLb to which the reference cells RMC0 and RMC2 are connected. The switch transistors T4 and T5 operate on bit line equalization signals EQ0 and EQ1, respectively.
In addition to the above-mentioned reference potential generation circuit, the semiconductor storage device having the conventional 1T/1C structure further comprises a reference control circuit to generate a control signal for the reference potential generation circuit and a sense amp circuit SA having word lines WL0 and WL1 and a plate line PL. The sense amp circuit SA is connected between one bit line BL and one bit complementation line BLb. These lines connect with a specified set of the reference cells RMC0 through RMC3 and a specified set of the memory cells MC0 through MC3. The sense amp circuit SA compares potentials generated on the respective bit lines with each other and amplifies a memory cell signal.
The following describes a read operation in the semiconductor storage device having the conventional 1T/1C structure. Here, power supply potential Vdd is assumed to be first data (data 1) and ground potential Vss is assumed to be second data (data 0). The example below explains an operation to read data from MC0 where data 1 is written.
When data is read from MC0 connected to the bit line BL0, the reference cells RMC1 and RMC3 are connected to the bit complementation line BLb0 supplied with the reference potential and to the bit complementation line BLb1 connected via BL0 and the switch transistor T4. For example, data 1 is already written to RMC1 via the reference write signal line RWSL1. Data 0 is already written to RMC3 via the reference write signal line RWSL0.
For the memory cell block containing MC0, a block selection signal goes active. In response to this block selection signal, the reference control circuit is activated.
The word line WL0 goes active and then the plate line PL0 goes active to select the memory cell MC0 connected to these lines. A potential corresponding to the data written in MC0 is applied to BL0. At the same time, the reference word line RWL0 and the reference plate line RPL go active. Since RMC1 and RMC3 are connected to these lines, a potential corresponding to data 1 written in RMC1 is applied to BLb0 and a potential corresponding to data 0 written in RMC3 is applied to BLb1.
Thereafter, the bit line equalization signal EQ0 is activated to operate the switch transistor T4 and connect BLb0 with BLb1. That is, BLb0 and BLb1 are short-circuited. Since the bit complementation lines BLb0 and BLb1 have almost the same capacity, the potential for each of BLb0 and BLb1 becomes an intermediate between potentials given to these bit complementation lines before the short circuit. This intermediate potential becomes the reference potential used to read data from the memory cell MC0.
After generating the reference potential on BLb0 in this manner, the reference control circuit inactivates EQ0 to disconnect BLb0 from BLb1. At the same time, the reference control circuit activates a sense amp circuit SA000. The sense amp circuit SA000 then amplifies the potential appearing on BL0 and corresponding to data 1 stored in MC0 and the reference potential appearing on BLb0. These amplified potentials are output as data to a digit line DB and a digit complementation line DBb.
In the conventional reference potential generation circuit, However, ferroelectric memory is used not only for a memory cell that stores data, but also for the reference cell that generates the reference potential. Moreover, the circuit is configured to always write the same data such as data 1->data 1->data 1-> . . . (data 0->data 0->data 0-> . . . ) in one reference cell. When data is repeatedly read from the memory cell, the polarization is always caused in the same direction on a ferroelectric film of a ferroelectric capacitor in the reference cell that generates the reference potential. As a result, there has been a problem of causing an imprint to deteriorate a polarization state of the ferroelectric film.
Furthermore, the conventional reference potential generation circuit is configured to connect a plurality of reference potential generation circuits to a single reference cell. Accordingly, when a block containing a memory cell to be selected is selected, data is written also to the reference cell connected to an inactive sense amp circuit.
Namely, the conventional reference cell for generating a reference potential is accessed more frequently than a memory cell where data is written and read. As a result, fatigue of the ferroelectric film is accelerated.